The present invention relates to a bus architecture for a packet-switched computer system which accommodates master, slave and memory devices having buses of various sizes, different from one another and different from the size of the system bus.
Computers are being designed today and for the foreseeable future with ever greater bus sizes, to handle the increasing throughput possible with very fast microprocessors. Typically, the bus architecture in a computer system is sized to accommodate the CPU, to allow for very fast transfers. For example, in today's workstations a databus width of 144 bits is common in high-end machines, while in the next generation of systems, databus widths of 288 bits will be used.
In today's systems, a bus having a width of a given number of bits requires that all functional units connected to the bus interface to that entire bus width. However, many devices are not designed to use the entire bus width, and hence there is waste of unused bandwidth. It is wasteful and expensive to design the functional units to accommodate the entire bus width when they cannot take advantage of it. (A reverse situation can also occur: functional devices such as memory may have bus widths larger than the databus width.)
A new type of system is needed wherein a large bus width does not require that functional units coupled to it be of the same bus size, and in particular that allows devices of smaller bus size to be coupled to a large-databus architecture without loss of data or inefficiencies through the loss of clock cycles or transmission of data that go unused because of bus size incompatibility.
Such a system must also accommodate devices coupled to the system bus that have bus sizes that are larger than that of the system bus.